hardware-Backed Resource-Access Isolation using ARM MTE and PAC

Overview

In-process compartmentalization can be achieved through hardware-enforced memory domains using ARM MTE (Memory Tagging Extension) and PAC (Pointer Authentication) ^[C002]. By assigning unique hardware tags to memory objects, the substrate binds unauthenticated requests to isolated resource domains ^[C000]. This approach targets the root cause of the bug rather than attempting to mitigate the late-stage effects of an exploit ^[C001]. This strategy mitigates path traversal and remote out-of-Memory (OOM) attacks by ensuring that any pointer attempting to access a resource outside its assigned hardware-tagged domain triggers an immediate fault [C000, C008].

This transition to hardware-backed isolation is critical because software-only memory safety is computationally prohibitive for high-performance environments. The viability of this substrate for cloud deployments is enabled by the ampereone processor (2024), which supports MTE with single-digit performance impact and zero memory capacity overhead for tag storage ^[C007].

However, the implementation must account for the trade-off between probabilistic and deterministic safety: MTE provides a low-friction path to safety but introduces new side-channels, such as "tiktag" gadgets that can leak MTE tags through speculative execution ^[C006]. To counter this, the substrate relies on formal ISA semantics—developed via tools like Sail—to provide a rigorous, executable model of processor behavior, ensuring that security primitives remain invariant across architectural states ^[C004].

Landscape

Current industry efforts to eliminate memory corruption divide into probabilistic tagging and deterministic capability-based architectures. Probabilistic schemes, such as ARM MTE and SPARC ADI, assign meta-information tags to memory objects to detect spatial and temporal violations [C000, C008]. Conversely, CHERI implements a hybrid capability-system that extends the RISC ISA and compiler to provide fine-grained hardware-enforced memory protection, offering superior scalability compared to traditional Memory-Management Unit (MMU) designs ^[C009].

Deployment is shifting toward datacenter-scale hardware and sandboxed runtimes. The AmpereOne processor is the first datacenter-class CPU to implement ARM MTE, providing synchronous tag-checking with low performance overhead ^[C007]. For WebAssembly (Wasm), which utilizes a flat memory model, hardware acceleration via MTE significantly reduces the overhead associated with software-only tagging ^[C005]. The Cage toolchain further optimizes this by combining MTE for spatial/temporal safety with ARM Pointer Authentication (PAC) to prevent the reuse of leaked pointers across Wasm instances ^[C003].

The efficacy of these hardware primitives is challenged by speculative execution and implementation gaps. The "tiktag" attack demonstrates that speculative execution can leak ARM MTE tags from arbitrary memory addresses, allowing attackers to bypass probabilistic defenses ^[C006]. To mitigate these architectural inconsistencies, researchers use Sail to create rigorous, executable ISA semantic models for ARMv8-A and CHERI-MIPS, providing a formal foundation for verifying that security primitives remain invariant across different processor states ^[C004].

Key Findings

Research indicates that the transition from software-defined memory safety to hardware-accelerated substrates is driven by a prohibitive "performance tax" on flat memory models. In WebAssembly (Wasm) environments, software-only memory tagging incurs runtime overheads between 48.91% (Wasm64) and 72.38% (Wasm32) ^[C005]. Implementing ARM MTE reduces these overheads to 5.71% for Wasm64 and 18.05% for Wasm32 ^[C005]. The Cage toolchain further optimizes this by combining MTE for spatial/temporal safety with Pointer Authentication (PAC) to prevent the reuse of leaked pointers, reducing overall runtime overhead to <5.8% ^[C003].

The evidence reveals a fundamental tension between probabilistic detection and deterministic prevention.

A critical discovery is that hardware tags can be transformed from defensive barriers into "speculative oracles." The TikTag attack demonstrates that speculative execution can leak MTE tags from arbitrary memory addresses with a success rate exceeding 95% in under four seconds ^[C006]. This allows attackers to bypass probabilistic defenses in the Linux kernel and Google Chrome by forging pointers that match the leaked tags ^[C006].

Regarding structural isolation, research shows that MTE and PAC can be retrofitted to implement capability-based in-process access control ^[C002]. To ensure these primitives remain invariant across architectural states, the use of executable ISA models like Sail is necessary to provide the formal semantics required for reasoning about security, though these models cannot eliminate RTL-level implementation bugs ^[C004].

Finally, temporal safety (Use-After-Free) remains the primary operational bottleneck ^[C008]. While MTE provides a production-viable probabilistic solution for temporal bugs ^[C007], deterministic alternatives often introduce "stop-the-world" pauses that are incompatible with real-time system requirements ^[C008].

Tensions and Tradeoffs

Practitioners implementing memory-safe substrates face a primary tension between probabilistic detection and deterministic prevention. ARM MTE offers a low-friction deployment path by assigning meta-information to memory objects ^[C000], but its small tag sizes introduce a collision probability that limits absolute protection guarantees ^[C000]. In contrast, CHERI eliminates entire vulnerability classes via a hybrid capability-system architecture but requires a prohibitive system-wide rebuild of the ISA, compiler, and operating system ^[C009].

A second tradeoff exists between software-defined safety and hardware acceleration. For the flat memory model of WebAssembly, pure software tagging implementations induce significant runtime overheads ^[C005]. Shifting these checks to ARM MTE-supported CPUs reduces the time overhead substantially ^[C005]. Furthermore, combining MTE with PAC (Pointer Authentication) can maintain low runtime overhead while providing both spatial and temporal safety for heap and stack allocations ^[C003].

However, hardware tags introduce a new speculative execution surface. The TikTag research demonstrates that speculative gadgets can leak MTE tags from arbitrary memory addresses ^[C006]. This transforms the hardware defense into a speculative "oracle," allowing attackers to bypass probabilistic protections in the Linux kernel and Google Chrome ^[C006].

Finally, there is a structural dependency between spatial and temporal safety. Many state-of-the-art mitigations for temporal corruption (e.g., Use-After-Free) require spatial safety to protect their own in-memory metadata ^[C008]. Without this external protection, temporal defenses remain vulnerable to evasion, yet adding the necessary spatial safety often increases the overall runtime overhead ^[C008].

Opportunities

Development Targets

To implement an MTE-backed isolation substrate, the following components require engineering:

• hardware-Tagged Request Domains: Build a request-dispatcher that assigns a unique ARM MTE tag to each unauthenticated request's memory region ^[C002]. By binding the request's execution context to a specific tag, the system can mitigate path traversal; any attempt to access memory outside the assigned "slice" triggers a hardware exception [C000, C007].
• PAC-Backed Pointer Guarding: Integrate ARM PAC to sign pointers within these slices, preventing attackers from leaking and reusing pointers across different request domains ^[C003].
• Low-Overhead WASM Runtimes: Develop a WebAssembly runtime utilizing MTE to replace software-based bounds checking to reduce the runtime overhead of memory safety for flat-memory models [C003, C005].
• Formal state Invariants: Use Sail to define formal ISA semantics for the isolation transitions, ensuring that security boundaries remain invariant across architectural states ^[C004].

Open Research Questions

• Speculative Leakage Mitigation: How can we prevent "tiktag" gadgets from leaking MTE tags through speculative execution ^[C006]?
• Tag Collision Probability: In high-concurrency environments, what is the precise statistical risk of tag collisions, and can "ephemeral" rotation of tags mitigate the "probabilistic lottery" inherent in MTE [C000, C008]?
• Optimization of the "Shim Tax": To what extent can the AmpereOne processor's zero-capacity overhead for tag storage be leveraged to eliminate the performance penalties of kernel-mode transitions during slice switching ^[C007]?

Architecture Trade-offs for Resource-Access Isolation

References

• [C000] Multi-Tag: A Hardware-Software Co-Design for Memory Safety based on Multi-Granular Memory Tagging — https://doi.org/10.1145/3579856.3590331
• [C001] Survey of security mitigations and architectures, December 2022 | memory_safety_blogpost_2022 — https://saaramar.github.io/memory_safety_blogpost_2022/
• [C002] Capacity: Cryptographically-Enforced In-Process Capabilities for Modern ARM Architectures — https://doi.org/10.1145/3576915.3623079
• [C003] Cage: Hardware-Accelerated Safe WebAssembly — https://doi.org/10.48550/arxiv.2408.11456
• [C004] ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS — https://doi.org/10.1145/3290384
• [C005] WebAssembly Memory Tagging — https://doi.org/10.1145/3733812.3765536
• [C006] TikTag: Breaking ARM's Memory Tagging Extension with Speculative Execution — https://doi.org/10.48550/arxiv.2406.08719
• [C007] Optimized Memory Tagging on AmpereOne Processors — https://openalex.org/W7106782640
• [C008] Understanding and mitigating memory corruption attacks — https://doi.org/10.17760/d20467218
• [C009] CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization — https://doi.org/10.1109/sp.2015.9